(a) Fields of the Invention
The present invention relates to semiconductor manufacturing apparatus for injecting impurities into semiconductor devices with insulating films.
(b) Description of Related Art
In recent years, thickness reduction of a gate insulating film as well as miniaturization of a semiconductor element has been advancing. Thus, the possibility is growing that the gate insulating film is damaged during device fabrication processes to cause dielectric breakdown.
For example, in an ion implantation process, an ion beam with a positively charged energy is directly implanted into a semiconductor element surface and a wafer (semiconductor substrate) surface, so that the surface of the formed semiconductor device is easily charged positively. If the charge quantity implanted by the ion beam exceeds a fixed value, that is, the breakdown charge quantity Qbd specific to a gate insulating film, breakdown of the insulating film occurs (see, for example, Hiroko KUBO et al., “Quantitative Charge Build-Up Evaluation Technique by Using MOS Capacitors with Charge Collecting Electrode in Wafer Processing”, IEICE Transactions on Electronics Vol. E79-C No. 2, pp. 198-205, February 1996). Since this device generally has a so-called antenna structure in which the area of a gate electrode portion is greater than the area of the gate insulating film, dielectric breakdown is likely to occur. Furthermore, this breakdown occurs more easily as the antenna ratio which is the ratio between the area of the gate electrode and the area of the gate insulating film is higher.
It is known that the breakdown by an ion beam occurs more easily as the beam current density during ion implantation is higher and that the breakdown occurs more significantly as the acceleration energy is higher. To deal with such characteristics, a proposal is made that the acceleration energy and the beam current as the ion implantation condition are set at values equal to or less than the breakdown charge quantity Qbd of the gate insulating film, thereby avoiding dielectric breakdown caused by charge build-up (see, for example, Japanese Unexamined Patent Publication No. H7-221306 (referred hereinafter to as Patent Document 1)).
On the other hand, a flood gun system is known which prevents positive charge build-up in the manner in which in order to prevent positive charge build-up induced by an ion beam, electrons together with the ion beam are supplied during ion implantation to neutralize positive charges. However, it is also known that since this flood gun system also supplies negative charges (electrons) directly to the surface of the semiconductor device, the resulting semiconductor surface is negatively charged to cause breakdown by negative charge build-up. To deal with such disadvantages, an approach is reported that energies of electrons supplied from the flood gun system are suppressed to a lower value, thereby reducing negative charge build-up of the surface of the semiconductor element to a fixed value equal to or less than the breakdown voltage (see, for example, Japanese Patent No. 3202002 (referred hereinafter to as Patent Document 2)).
Although the approach disclosed by Patent Document 2 reduces breakdown of the gate insulating film caused by negative charge build-up resulting from the flood gun system, breakdown of the gate insulating film caused by positive charge build-up resulting from the ion beam is still not completely prevented. The reason for this is as follows: even though electrons are supplied from the flood gun system during ion implantation, the potential at the moment when the ion beam is radiated onto the wafer is not completely neutralized and the potential distribution determined by the ion beam and the electrons is still present thereon. Therefore, as described above, charge build-up occurs depending on not only the beam current and the acceleration energy of the ion beam but also the scanning speed of the ion beam onto the wafer. Among others, the inventors found that the charge build-up condition by the ion beam greatly differs depending on the beam scanning speed.
Beam scanning methods include: the method in which with a wafer fixed, an ion beam is electrostatically or electromagnetically scanned two-dimensionally in X-Y directions; the method in which with an ion beam electrostatically or electromagnetically scanned one-dimensionally in one direction, a wafer is subjected to mechanical scanning in the perpendicular direction to the ion beam scanning direction and one-dimensionally in one direction; and the r-θ scanning method in which while an ion beam is fixed and a rotating disk with a wafer held thereon is being rotated, one-dimensional scanning is carried out in the radial direction of the disk. Other than these methods, various types of methods, such as the method in which with an ion beam fixed, a wafer is subjected to mechanical scanning two-dimensionally in X-Y directions, are used. Therefore, the relative linear speed between the ion beam and the wafer greatly differs depending on a beam scanning method used. As shown above, since various types of scanning speeds ranging from an extremely low-speed scanning to an extremely high-speed scanning are present, a method for reducing positive charge build-up regardless of these scanning speeds and methods is demanded.